A Flexible and Expendable Neuroimage Processor Architecture
نویسندگان
چکیده
An analog versatile neuroimage processor (VNIP) architecture is proposed here. VNIP can process various types of neural network and image processing structures, without any hardware modification. The structure allows unlimited expansion of network size and the compensation of process variation. The proof-of-concept chip is implemented, using a combination of continuous-time multiplier and switched-capacitor techniques. The throughput is 12 106 synapses/s mm2 and the energy consumption is 10 9 J/synapse. A test chip was fabricated, using a 1.2m double-poly CMOS process and tested, verifying the flexibility and expandability of the architecture.
منابع مشابه
Ultra-Low-Energy DSP Processor Design for Many-Core Parallel Applications
Background and Objectives: Digital signal processors are widely used in energy constrained applications in which battery lifetime is a critical concern. Accordingly, designing ultra-low-energy processors is a major concern. In this work and in the first step, we propose a sub-threshold DSP processor. Methods: As our baseline architecture, we use a modified version of an existing ultra-low-power...
متن کاملAn Effective Hybrid Genetic Algorithm for Hybrid Flow Shops with Sequence Dependent Setup Times and Processor Blocking
Hybrid flow-shop or flexible flow shop problems have remained subject of intensive research over several years. Hybrid flow-shop problems overcome one of the limitations of the classical flow-shop model by allowing parallel processors at each stage of task processing. In many papers the assumptions are generally made that there is unlimited storage available between stages and the setup times a...
متن کاملSensitivity Analysis of ProSEDS (Propulsive Small Expendable Deployer System) Data Communication System
This paper discusses analytical approaches to evaluating performance of Spacecraft On-Board Computing systems, thereby ultimately achieving a reliable spacecraft data communications systems. The sensitivity analysis approach of memory system on the ProSEDS (Propulsive Small Expendable Deployer System) [I] as a part of its data communication system will be investigated. Also, general issues and ...
متن کاملParallel Architecture for Flexible Approximate Text Searching
This paper presents a processor array design for flexible approximate string matching. Initially, a sequential algorithm is discussed which consists of two phases, i.e. preprocessing and searching. Then, starting from the computational schedule of the searching phase a parallel architecture is derived. Further, the preprocessing phase is also accomodated onto the same architecture. Key-Words: A...
متن کاملDesign and Implementation of Field Programmable Gate Array Based Baseband Processor for Passive Radio Frequency Identification Tag (TECHNICAL NOTE)
In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix C...
متن کامل